HDLC Coder-Decoder

Software Overview

ILLICO is offering HDLC Encoder and Decoder functions in 'C' language and in a highly optimized assembly language version for the TMS320C54x family.
The HDLC Encoder processes the user supplied input bytes and generates the HDLC output bit stream, which consists of:

  • Initial flags: a (user-defined) number of repeated 01111110 sequence.
  • One or more frames, containing the user-supplied data. Each time 5 consecutive 1's are present, the encoder inserts a 0. When the user indicates that the current frame is over, the HDLC Encoder inserts the 16 bit CRC in the HDLC bit stream.
  • Interframe flag: the frames are separated by a user-defined number of flags.

The HDLC Decoder takes an HDLC bit stream as input and performs flag detection, 0 bit deletion and FCS checking. The extracted frame data bytes are passed to the output.

Available Products

  • ANSI standard 'C' language HDLC encoder/decoder functions.
  • TMS320C54x assembly language HDLC encoder/decoder functions.

Features and Benefits

  • Software available in 'C' or optimized C54x assembly language versions.
  • C54x version has a 'C' language interface for ease of installation on user's platform.
  • Multiple HDLC channels can run on the same processor.
  • Easily installed on user's platform: the Software does not use the processor's hardware ressources such as timers, interrupts, I/O ports and other peripheral control registers.
  • Detailed Interface Specification

Processor Resource Requirements (TMS320C54x assembly version)
For HDLC encoder:

Program Memory: 650 words
Data Memory: 16 words per encoder channel
Execution time: about 8 cycles per output bit

For HDLC decoder:

Program Memory: 650 words
Data Memory: 16 words per encoder channel
Execution time: about 17 cycles per output bit


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